DDR5 Testbed
This project contains open hardware design files for an experimental test module in the mechanical form factor of SO-DIMM. The module includes a single DDR5 RAM IC with all signals break-routed in the SO-DIMM edge connector. The board has been designed to target Micron MT60B2G8HB-48B:A 16Gb DRAM. The design files were prepared in KiCad 9.x. Please note that this board is not electrically compatible with off-the-shelf SO-DIMM DDR memory modules. It is compatible with this experimental testing platform.
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DDR5 Testbed
Copyright (c) 2022-2025 Antmicro
Overview
This project contains open hardware design files for an experimental test module in the mechanical form factor of SO-DIMM. The module includes a single DDR5 RAM IC with all signals break-routed in the SO-DIMM edge connector. The board has been designed to target Micron MT60B2G8HB-48B:A 16Gb DRAM. The design files were prepared in KiCad 9.x. Please note that this board is not electrically compatible with off-the-shelf SO-DIMM DDR memory modules. It is compatible with this experimental testing platform.
Project structure
The main project directory contains KiCad PCB project files, a LICENSE and a README. The remaining files are stored in the following directories:
img- contains graphics for this READMEdoc- contains schematics in PDF form
License
This project is published under the Apache-2.0 license.
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