Chisel AXI peripheral example

This repository holds an example of simple AXI-Lite peripheral implemented with Chisel3. To generate a Verilog simply run make in the top level directory.

Contributors
1

Created
6 years ago

Repo
Antmicro's Github antmicro/simple-chisel-axi-peripheral

License
Apache-2.0

Languages

scala(95.58%)

markdown(3.30%)

makefile(1.12%)

Chisel AXI peripheral example

This repository holds an example of simple AXI-Lite peripheral implemented with Chisel3. To generate a Verilog simply run make in the top level directory.

chisel
axi
ip
fpga

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Chisel AXI peripheral example

Chisel AXI peripheral example

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